1. Field of the Invention
The present invention relates to a display apparatus. More specifically, the invention relates to a technology effectively applied to a liquid crystal display apparatus.
2. Description of Related Art
Conventionally, display apparatuses include a liquid crystal display apparatus using a liquid crystal display panel. The liquid crystal display panel uses apair of substrates between which a liquid crystal material is sealed. The substrate is provided with multiple gate lines and drain lines in a matrix, for example. Two adjacent gate lines and two adjacent drain lines enclose an area, i.e., one pixel area. Each pixel area contains a TFT element or a pixel electrode.
The liquid crystal display panel displays an image or a video, for example, by supplying each drain line with a display data signal and sequentially supplying each gate line with a scanning signal.
A timing controller and a data driver (drain driver) are used to generate a display data signal input to each drain line and control an input timing. The timing controller and a scanning driver (gate driver) are used to generate a scanning signal input to each gate line and control an input timing.
For example, the data driver includes: a latch circuit for holding display data until it is accumulated to become large enough for one horizontal synchronization period; a level shift circuit for converting a signal level of the display data; a decoder circuit for generating an analog signal (gradation voltage) based on the display data provided with the converted signal level; an output circuit for amplifying the analog signal generated from the decoder circuit; and a switch circuit for outputting the analog signal amplified by the output circuit to a drain line (e.g., see patent document 1).
The level shit circuit is a voltage conversion circuit and is constructed to include two stages, i.e., a low-voltage operating unit and a high-voltage operating unit. The high-voltage operating unit uses a so-called cross-coupled circuit construction that includes, for example, four or six MOS transistors (e.g., see patent document 2).
Recently, there is proposed a method of inserting a black display between display data for the liquid crystal display apparatus so as to improve the moving picture quality (e.g., see patent document 3).
[Patent document 1] Japanese Patent Laid-Open No. 2004-301946
[Patent document 2] Japanese Patent Laid-Open No. 2004-289329
[Patent document 3] Japanese Patent Laid-Open No. 2003-208599
However, the inventors found that the conventional liquid crystal display apparatus causes the following problems.
(a) The data driver outputs a display data signal to all drain lines at the same timing. However, the scanning signal causes different waveforms for a pixel near a scanning signal input terminal for the gate line and for a pixel far from the same. There is a variation in times to write display data signals (gradation voltage signals) for TFT elements.
(b) The data driver causes a momentary current at a timing when a horizontal synchronization signal latches data at a time. A power supply voltage fluctuates due to the momentary current to degrade the reliability of the data driver and the display apparatus.
(c) When the scanning driver may include multiple driver ICs, an interval greater than or equal to an interval between chips needs to be provided between the gate line for outputting a scanning signal for the display data and the gate line for outputting a scanning signal for black display insertion. This is because two gate lines connected to the same driver IC cannot be controlled so as to output a scanning signal for display data to one gate line and to output a scanning signal for black data insertion to the other. When multiple driver ICs are cascade-connected, there is a limitation on setting of an interval between the gate line for display data and the gate line for black data insertion.
(d) The driver supplies a very higher voltage to the TFT element than an operating voltage for a logic circuit previous to a shift register and cannot operate with a MOS transistor size for a conventional level shifter circuit. Operating the level shifter requires a MOS transistor double or larger than a conventional one. Accordingly, the driver IC becomes larger.
To be more specific, the problem in (a) occurs for the following reason. While a scanning signal input to the gate line generates a sharp waveform near the input terminal, the waveform becomes duller as the distance from the input terminal increases. Since the conventional data driver outputs a display data signal to respective drain lines at a time, the write timing is set at a point near to or far from the input terminal of the gate line. A write operation becomes insufficient at the near point or the far point. The display quality degrades accordingly.
The following describes the problem in (b) more specifically. The data driver allows the horizontal synchronization signal to output data from a latch circuit at a time. The output data simultaneously drives a level shifter circuit to select a specified gradation voltage for a decoder circuit. At this time, the level shifter circuit applies an electric current equivalent to the number of outputs between the power supply for a high withstand voltage system (high-voltage operating unit) and a ground (GND). Increasing the number of outputs accordingly increases the momentary current and a variation in the power supply voltage. Such problem is remarkable with respect to an onboard liquid crystal display apparatus such as a car navigation system, for example.